Novel Test Methods for NPSF Faults in SRAM

NPSF (Neighborhood Pattern Sensitive Faults) involves with three or more cells in the memory. These NPSF fault models are recognized as high quality fault models for memory arrays. The excessive test algorithm time lost associated with its compared to other fault models restricts its adoption for memory testing. The existing methodology for NPSF fault detection using CA (Cellular Automata) with Hamiltonian sequence is inadequate due to long test time and deficient in complete fault detection. In order to improve the fault detection further, an extensive test method is proposed in our work that uses binary and gray sequences along with existing Hamiltonian series in the CA test environment. Since CA uses set of rules, 256 such rules are considered in the combination of 28 i.e., 00000000 to 11111111. These rules are applied in parallel while writing each Hamiltonian or gray or binary bit pattern on the chosen memory structure. It is observed that the speed of fault detection is improved by 29% and 44% using Gray and binary series respectively at the cost of area overhead in terms of number of slice LUT’s which are raised by 15% when compared with existing Hamiltonian series. The key advantage of using Gray and binary is that the fault free test pattern arises at rule 60 and 204 respectively. Whereas using Hamiltonian, it is required to wait until rule 225 to arise fault free condition.