深亚微米集成电路信号完整性实验表征的合作研究

1999 IEEE International Symposium on Electromagnetic Compatability. Symposium Record (Cat. No.99CH36261) Pub Date : 1999-08-02 DOI:10.1109/ISEMC.1999.812928

E. Sicard, S. Delmas, F. Caignet, R. De Smedt, T. Steinecke, J. Ferrante, P. Saintot

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引用次数: 6

摘要

下面的论文描述了一个欧洲四大工业和一个学术机构之间的合作项目，旨在开发一种用于精确表征信号完整性的新型测量方法。该方法已在0.35、0.25和0.18 /spl mu/m CMOS技术上实现，并从几个方面研究了信号完整性:互连延迟、互连内串扰、串扰引起的延迟和供电线路波动。本文详细介绍了该方法和项目的里程碑。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A cooperative research for experimental characterization of signal integrity in deep submicron integrated circuits

The following paper describes a cooperative project between four major European industries and one academic institute, on the development of a novel measurement method for the precise characterization of signal integrity. The method has been implemented in 0.35, 0.25 and 0.18 /spl mu/m CMOS technology, and several aspects of signal integrity have been investigated: interconnect delay, crosstalk within interconnects, delay induced by crosstalk and power supply lines fluctuations. Details on the method and the milestones of the project are reported in the paper.

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来源期刊

1999 IEEE International Symposium on Electromagnetic Compatability. Symposium Record (Cat. No.99CH36261)

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