An Ultra Low Power, 3-Wire Serial Interface Design for Data Converters in Pin-Constrainted Applications with 180 nm CMOS Technology

In this paper, an ultra low power, small area, fully synthesizable, 3-wire serial interface is presented for data converters in the pin-constrainted applications. The synchronous parallel to serial (P2S) interface transforms the data converters parallel samples to serial stream for reducing the number of required pins. On the other hand, the synchronous serial to parallel (S2P) interface reconstructs the parallel samples. Depending on the pin constraints and data rate requirements, different configurations are also proposed for multi-channel interfaces. Two operating modes are incorporated for different synchronization schemes. The proposed serial interface design is effective to minimize the number of required PADs, diminish the die area and decrease the printed circuit board (PCB) complexity. The design is integrated in a five channel analog front end (AFE) with one of the proposed configuration for ultrasonic sensor and it is fabricated with 180 nm CMOS technology. By using this serial interface design, the required pin reduction is 85.25% and 100% throughput is achievable. The P2S and S2P occupy a very small area of 6671 μm2 and both requires only 760 gates for implementation. The total current consumption is upto 102 μA from 1.8 V power supply and only 157 μW power for full operation is needed. The simulation and measurement results verify the functional accuracy and rigorousness of the proposed design with both operating modes and adopted configuration.