Optimized multicore architectures for data parallel fast Fourier transform

In this paper, we propose optimized multicore designs for data parallel Fast Fourier Transform (FFT) applications. FFT is widely used in digital systems as a fundamental algorithm. The implementation of FFT on conventional architectures has been studied. However, the evaluation of data parallel FFT in Network-on-Chip (NoC) platforms has not been well addressed. We analyse data parallel FFT in terms of on-chip traffic patterns. NoC designs optimized for FFT are introduced. Experiments show that, the execution times of our optimized designs are 12.1% and 18.3% shorter than the original NoC design.