Q-SegNet: Quantized deep convolutional neural network for image segmentation on FPGA

One of the important tasks in the area of computer vision is semantic segmentation. The implementation of a semantic segmentation system in an embedded platform is a fruitful idea. But due to the limitations of embedded ability, it becomes a tough task. In this article, we proposed a novel and practical architecture i.e. quantized deep convolutional neural network for image segmentation (Q-SegNet). This architecture will be implemented on an FPGA device, which allows reducing the parameter size of the original architecture. Hence the required power also reduces. Thus, this paper proposed a high performance deep learning processor unit (DPU) based accelerator for Semantic segmentation neural network. This research is quite suitable for robot vision in an embedded platform and the segmentation accuracy is up to 89.60% on average. Notably, the proposed faster architecture is ideal for low power embedded devices that need to solve the shortest path problem, path searching, and motion planning, in the ADAS and Robot.