{"title":"基于FPGA不同输入输出标准的绿色数据处理器件设计","authors":"Diya Garg, K. Sharma, Anshu Singla","doi":"10.1109/PDGC.2018.8745716","DOIUrl":null,"url":null,"abstract":"An effective way to save power is utilization of suitable Input/output (IO) standard with Data Processing Devices (DPDs) implemented on Field Programmable Gate Arrays (FPGAs) at data centers. In this work, a power efficient Floating Point Unit (FPU) as a DPD has been designed in 65nm process technology using Virtex 5 FPGA and its impact on the power consumption of FPU with different IO standards is presented. The performance was analyzed at 1.9 GHz frequency which is operating frequency of AMD X2150 using Verilog as hardware descriptive language (HDL) in Xilinx 14.1 ISE platform. Among all the reported IO standards used with FPU at 1.9 GHz, the results obtained with Low-Voltage Digitally Controlled Impedance_15 (LVDCI_15) shows power consumption of 2.169W only. Using LVDCI_15 instead of Stub-Series Terminated Logic_I (SSTL_I), saves 39.44% of total power at operating frequency of 1.9 GHz. LVDCI15 is best suitable with Virtex 5 FPGA at 1.9 GHz for implementation of DPDs.","PeriodicalId":303401,"journal":{"name":"2018 Fifth International Conference on Parallel, Distributed and Grid Computing (PDGC)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Designing a Green Data Processing Device using Different Input/Output Standards on FPGA\",\"authors\":\"Diya Garg, K. Sharma, Anshu Singla\",\"doi\":\"10.1109/PDGC.2018.8745716\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An effective way to save power is utilization of suitable Input/output (IO) standard with Data Processing Devices (DPDs) implemented on Field Programmable Gate Arrays (FPGAs) at data centers. In this work, a power efficient Floating Point Unit (FPU) as a DPD has been designed in 65nm process technology using Virtex 5 FPGA and its impact on the power consumption of FPU with different IO standards is presented. The performance was analyzed at 1.9 GHz frequency which is operating frequency of AMD X2150 using Verilog as hardware descriptive language (HDL) in Xilinx 14.1 ISE platform. Among all the reported IO standards used with FPU at 1.9 GHz, the results obtained with Low-Voltage Digitally Controlled Impedance_15 (LVDCI_15) shows power consumption of 2.169W only. Using LVDCI_15 instead of Stub-Series Terminated Logic_I (SSTL_I), saves 39.44% of total power at operating frequency of 1.9 GHz. LVDCI15 is best suitable with Virtex 5 FPGA at 1.9 GHz for implementation of DPDs.\",\"PeriodicalId\":303401,\"journal\":{\"name\":\"2018 Fifth International Conference on Parallel, Distributed and Grid Computing (PDGC)\",\"volume\":\"262 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 Fifth International Conference on Parallel, Distributed and Grid Computing (PDGC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PDGC.2018.8745716\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Fifth International Conference on Parallel, Distributed and Grid Computing (PDGC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PDGC.2018.8745716","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Designing a Green Data Processing Device using Different Input/Output Standards on FPGA
An effective way to save power is utilization of suitable Input/output (IO) standard with Data Processing Devices (DPDs) implemented on Field Programmable Gate Arrays (FPGAs) at data centers. In this work, a power efficient Floating Point Unit (FPU) as a DPD has been designed in 65nm process technology using Virtex 5 FPGA and its impact on the power consumption of FPU with different IO standards is presented. The performance was analyzed at 1.9 GHz frequency which is operating frequency of AMD X2150 using Verilog as hardware descriptive language (HDL) in Xilinx 14.1 ISE platform. Among all the reported IO standards used with FPU at 1.9 GHz, the results obtained with Low-Voltage Digitally Controlled Impedance_15 (LVDCI_15) shows power consumption of 2.169W only. Using LVDCI_15 instead of Stub-Series Terminated Logic_I (SSTL_I), saves 39.44% of total power at operating frequency of 1.9 GHz. LVDCI15 is best suitable with Virtex 5 FPGA at 1.9 GHz for implementation of DPDs.