Si:HfO2 FeRAM阵列中的内存窗口:高级节点的性能改进和外推

2023 IEEE International Memory Workshop (IMW) Pub Date : 2023-05-01 DOI:10.1109/IMW56887.2023.10145972

J. Laguerre, M. Bocquet, O. Billoint, S. Martin, J. Coignus, C. Carabasse, T. Magis, T. Dewolf, F. Andrieu, L. Grenouillet

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引用次数: 0

摘要

通过刻蚀铁电电容器(FeCAP)的铁电(FE)膜，表明beol集成的基于Si: hfo2的16kbit ITIC FeRAM阵列的记忆窗口(MW)得到了显著改善(×3)。为了估计先进技术节点上较大阵列的MW演变，开发了基于Preisach电流的紧凑模型，根据测量的FeCAP电气特性进行校准，并在各种工作电压下进行验证。使用西门子Eldo对ITIC 16kbit FeRAM阵列结构进行的电气模拟表明，在先进技术节点上缩放晶体管(1T)对MW有利。低电压应用也要求FE薄膜厚度降低到10nm以下。

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Memory Window in Si:HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes

The Memory Window (MW) of BEOL-integrated Si:HfO2-based 16kbit ITIC FeRAM arrays is shown to be significantly improved (×3) by etching the ferroelectric (FE) film of the Ferroelectric CAPacitor (FeCAP). To estimate the MW evolution in larger arrays at advanced technology nodes, a Preisach current-based compact model is developed, calibrated on measured FeCAP electrical characteristics and validated at various operating voltages. Electrical simulations of an elementary ITIC 16kbit FeRAM array-like structure using Siemens Eldo show that scaling the transistor (1T) at advanced technology nodes can be beneficial for the MW. FE film thickness reduction below 10nm will also be requested for low voltage applications.

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2023 IEEE International Memory Workshop (IMW)

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