40nm CMOS 50G PON光接收器前端

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI:10.1109/ICTA56932.2022.9962967

Nianquan Ran, Jia Li, Shuaizhe Ma, Yuye Yang, Wanqing Zhao, Hao Li, Dan Li

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引用次数: 0

摘要

随着50Gb/s PON通信网络标准的确定，对50Gb/s PON芯片的需求很大。本文设计了一款功耗极低的50Gb/s跨阻放大器(TIA)芯片，采用40nm标准CMOS工艺，大大降低了制造成本。在高增益模式下，跨阻增益为66.0dBΩ，带宽为30.4GHz。在低增益模式下，通阻为52.4dBΩ，带宽为34.1GHz。输入信号范围最大可达2mA，最大差分输出摆幅440mVpp。接收机前端电路功耗23.4mW，能量效率0.47pJ/bit。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optical Receiver Front-End for 50G PON in 40nm CMOS

With the determination of the 50Gb/s PON communication network standard, there is a large demand for 50Gb/s PON chips. In this paper, we design a 50Gb/s transimpedance amplifier (TIA) chip with very low power consumption, which greatly reduces the manufacturing cost by adopting the 40nm standard CMOS process. In the high gain mode, the transimpedance gain is 66.0dBΩ and the bandwidth is 30.4GHz. In the low gain mode, the transimpedance is 52.4dBΩ and the bandwidth is 34.1GHz. The input signal range can reach 2mA at most and the maximum differential output swing is 440mVpp. The receiver front-end circuit consumes 23.4mW, and the energy efficiency is 0.47pJ/bit.

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来源期刊

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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