{"title":"用于分析块数据流体系结构的可编程模拟器","authors":"S. Alexandre, W. Alexander, D. Reeves","doi":"10.1109/MASCOT.1994.284391","DOIUrl":null,"url":null,"abstract":"A programmable simulator has been developed for analyzing the performance of a class of parallel computers. The simulator provides detailed information about the timing, resource usage, and output results for an algorithm executing on the parallel computer. A user specifies the configuration and performance characteristics of the computer to be simulated. The user also describes the algorithm to be executed on the computer. The use of the simulator for QR factorization is briefly described and the results are presented. Our approach is compared with other simulation methods.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A programmable simulator for analyzing the block data flow architecture\",\"authors\":\"S. Alexandre, W. Alexander, D. Reeves\",\"doi\":\"10.1109/MASCOT.1994.284391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A programmable simulator has been developed for analyzing the performance of a class of parallel computers. The simulator provides detailed information about the timing, resource usage, and output results for an algorithm executing on the parallel computer. A user specifies the configuration and performance characteristics of the computer to be simulated. The user also describes the algorithm to be executed on the computer. The use of the simulator for QR factorization is briefly described and the results are presented. Our approach is compared with other simulation methods.<<ETX>>\",\"PeriodicalId\":288344,\"journal\":{\"name\":\"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-01-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MASCOT.1994.284391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MASCOT.1994.284391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A programmable simulator for analyzing the block data flow architecture
A programmable simulator has been developed for analyzing the performance of a class of parallel computers. The simulator provides detailed information about the timing, resource usage, and output results for an algorithm executing on the parallel computer. A user specifies the configuration and performance characteristics of the computer to be simulated. The user also describes the algorithm to be executed on the computer. The use of the simulator for QR factorization is briefly described and the results are presented. Our approach is compared with other simulation methods.<>