A Survey on Hardware Implementation of Cryptographic Algorithms Using Field Programmable Gate Array

In the past recent years the idea towards secure data communication is increasing day by day. The secure communication is being achieved by applying various cryptographic algorithms on the data which is to be transferred over wireless networks. The different cryptographic algorithms that are generally practiced in the current cyber world are Advanced Encryption Standard (AES), Data Encryption Standard (DES), RSA algorithm, Message Digest 5 (MD5), Secure Hash Algorithm (SHA). All these algorithms are highly secured with sound and complex mathematical computations that makes the hacker tedious to breach the data which is protected by these algorithm. The hardware implementation of algorithms enhances the speed, efficiency and reliability of security standards. In this work the Field Programmable Gate Array (FPGA) implementation of various cryptographic algorithms is discussed in details. The main motivation behind the FPGA implementations of Security algorithms is to increase the speed and decrease delays of software implementations. There are millions of logic gates that are clustered in FPGA, this brings new innovations to existing algorithms. This paper surveyss the parameters such as throughput, operating frequency, number of slice registers used and number of clock cycles of FPGA that have the major role in execution process of cryptographic algorithms. Comparative analysis on hardware implementation of security algorithms on different FPGA’s is also done.