S. Clerc, F. Abouzeid, F. Argoud, Abhay Kumar, R. Kumar, P. Roche
{"title":"一个240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252位帧解码器采用超低压电路设计平台","authors":"S. Clerc, F. Abouzeid, F. Argoud, Abhay Kumar, R. Kumar, P. Roche","doi":"10.1109/ICECS.2011.6122228","DOIUrl":null,"url":null,"abstract":"A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0°C to 50°C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4× down to 0.24V, reducing the dynamic power by a factor 14× versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform\",\"authors\":\"S. Clerc, F. Abouzeid, F. Argoud, Abhay Kumar, R. Kumar, P. Roche\",\"doi\":\"10.1109/ICECS.2011.6122228\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0°C to 50°C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4× down to 0.24V, reducing the dynamic power by a factor 14× versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122228\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122228","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform
A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0°C to 50°C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4× down to 0.24V, reducing the dynamic power by a factor 14× versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.
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