模拟不完善的生产测试对可重构VLSI芯片的影响

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208149

B. Ciciani

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引用次数: 0

摘要

提出了一种新的“表观”良率评价方法。通过这种方法，可以在测试和重新配置阶段结束时评估制造过程的质量和真正好芯片的预期比例。它允许具有和不具有冗余的容错VLSI芯片(或WSI系统)的表征。它易于使用，并且允许对收益率值的近似水平进行预测

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Modeling the effects of imperfect production testing on reconfigurable VLSI chips

An innovative method for the 'apparent' yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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