一个12.5 ns 16 Mb CMOS SRAM

Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI:10.1109/VLSIC.1993.920562

K. Ishibashi, K. Komiyaji, S. Morita, Toshiro Aoto, S. Ikeda, K. Asayama, Atsuyosi Koike, T. Yamanaka, N. Hashimoto, Haruhito Iida, F. Kojima, Koichi Motohashi, K. Sasaki

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引用次数: 22

摘要

高速电路、高产量冗余技术和软误差免疫细胞是实现超高密度静态ram的关键。报道了一种采用0.4 /spl mu/m CMOS技术制造的16mb (4Mx4/2Mx8) CMOS SRAM。采用共质心几何(CCG)布局感测放大器和分路数据总线结构，在3.3 V供电电压下实现了12.5 ns的地址访问时间。在16mb SRAM中加入了一种高效率且无存取损失的灵活冗余技术(FRT)。7.16 /spl mu/m/sup 2/ TFT负载传感器采用堆叠电容，即使在3.3 V电源电压下也能实现软误差抗抗。

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A 12.5 ns 16 Mb CMOS SRAM

A high-speed circuit, a high-yield redundancy technique, and a soft-error immune cell are essential to realize ultra high density static RAMs. A 16 Mb (4Mx4/2Mx8) CMOS SRAM fabricated using 0.4 /spl mu/m CMOS technology is reported. An address access time of 12.5 ns is attained with 3.3 V supply voltage by using a common-centroid-geometry (CCG) layout sense amplifier and divided data bus architecture. A flexible redundancy technique (FRT) with high efficiency and with no access penalty has been incorporated into the 16 Mb SRAM. A 7.16 /spl mu/m/sup 2/ TFT load cell with stacked capacitors, achieves soft-error immunity even for the supply voltage of 3.3 V.

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Symposium 1993 on VLSI Circuits

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