{"title":"几种超标量处理器模型与VLIW处理器的性能比较","authors":"John Lenell, N. Bagherzadeh","doi":"10.1109/IPPS.1993.262853","DOIUrl":null,"url":null,"abstract":"This paper quantitatively compares various superscalar processor architectures with a very long instruction word architecture developed at the University of California, Irvine. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each.<<ETX>>","PeriodicalId":248927,"journal":{"name":"[1993] Proceedings Seventh International Parallel Processing Symposium","volume":"127 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A performance comparison of several superscalar processor models with a VLIW processor\",\"authors\":\"John Lenell, N. Bagherzadeh\",\"doi\":\"10.1109/IPPS.1993.262853\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper quantitatively compares various superscalar processor architectures with a very long instruction word architecture developed at the University of California, Irvine. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each.<<ETX>>\",\"PeriodicalId\":248927,\"journal\":{\"name\":\"[1993] Proceedings Seventh International Parallel Processing Symposium\",\"volume\":\"127 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1993] Proceedings Seventh International Parallel Processing Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPPS.1993.262853\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993] Proceedings Seventh International Parallel Processing Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPPS.1993.262853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A performance comparison of several superscalar processor models with a VLIW processor
This paper quantitatively compares various superscalar processor architectures with a very long instruction word architecture developed at the University of California, Irvine. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each.<>