使用参数时间自动机形式化Time4sys

2019 International Symposium on Theoretical Aspects of Software Engineering (TASE) Pub Date : 2019-05-23 DOI:10.1109/TASE.2019.000-3

É. André

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引用次数: 1

摘要

必须对关键的实时系统进行验证，以避免发生故障时产生严重后果的风险。泰雷兹开发了一种开放的形式主义“Time4Sys”来模拟实时系统，具有表达性特征，如周期性或零星任务、任务依赖性、分布式系统等。然而，Time4Sys本身不允许形式推理。在这项工作中，我们提出了从Time4Sys到(参数)定时自动机的转换，以便允许形式化验证。

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Formalizing Time4sys using parametric timed automata

Critical real-time systems must be verified to avoid the risk of dramatic consequences in case of failure. Thales developed an open formalism "Time4Sys" to model real-time systems, with expressive features such as periodic or sporadic tasks, task dependencies, distributed systems, etc. However, Time4Sys does not natively allow for a formal reasoning. In this work, we present a translation from Time4Sys to (parametric) timed automata, so as to allow for a formal verification.

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2019 International Symposium on Theoretical Aspects of Software Engineering (TASE)

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