CMOS加法器的功耗估算

T. K. Callaway, E. Swartzlander
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引用次数: 59

摘要

本文研究了六种类型的加法器,试图对其功耗进行建模。结果表明,与更复杂的模型和电路的物理实现相比,使用相对简单的模型提供了定性准确的结果。简单模型和物理测量之间的主要差异似乎是假设所有门在开关时消耗相同的功率,而不管它们是风扇输入还是风扇输出。由于进位前瞻加法器有多个扇出和扇入大于2的门,因此简单模型低估了其功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Estimating the power consumption of CMOS adders
Six types of adders are examined in an attempt to model their power dissipation. It is shown that the use of a relatively simple model provides results that are qualitatively accurate, when compared to more sophisticated models and to physical implementations of the circuits. The main discrepancy between the simple model and the physical measurements seems to be the assumption that all gates will consume the same amount of power when they switch, regardless of their fan-in or fanout. Because the carry lookahead adder has several gates with a fan out and fan-in higher than two, the simple model underestimates its power dissipation.<>
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