一个22.8 GHz至32.8 GHz紧凑型功率放大器,输出P1dB为15 dBm,峰值PAE为36.5%,采用65nm CMOS

Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, W. Deng, B. Chi, Zhihua Wang
{"title":"一个22.8 GHz至32.8 GHz紧凑型功率放大器,输出P1dB为15 dBm,峰值PAE为36.5%,采用65nm CMOS","authors":"Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, W. Deng, B. Chi, Zhihua Wang","doi":"10.1109/ICTA56932.2022.9963053","DOIUrl":null,"url":null,"abstract":"A CMOS broadband millimeter-wave power amplifier (PA) based on a Sandwiched Transformer (ST) output matching network is presented in this paper. The ST output matching network with a three-layer structure providing a larger coupling coefficient (k) than the traditional two-layer stack structure is proposed for PA's output matching network. The layout of the transistors is optimized to improve the PA's performance. Fabricated in 65-nm CMOS process, the PA has achieved 15 dBm OP1dBand 36.5% peak power added efficiency (PAE). The 3-dB bandwidth of the PA is from 22.8 GHz to 32.8 GHz.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS\",\"authors\":\"Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, W. Deng, B. Chi, Zhihua Wang\",\"doi\":\"10.1109/ICTA56932.2022.9963053\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS broadband millimeter-wave power amplifier (PA) based on a Sandwiched Transformer (ST) output matching network is presented in this paper. The ST output matching network with a three-layer structure providing a larger coupling coefficient (k) than the traditional two-layer stack structure is proposed for PA's output matching network. The layout of the transistors is optimized to improve the PA's performance. Fabricated in 65-nm CMOS process, the PA has achieved 15 dBm OP1dBand 36.5% peak power added efficiency (PAE). The 3-dB bandwidth of the PA is from 22.8 GHz to 32.8 GHz.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963053\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种基于夹层变压器输出匹配网络的CMOS宽带毫米波功率放大器。针对PA的输出匹配网络,提出了具有三层结构的ST输出匹配网络,其耦合系数(k)大于传统的两层堆叠结构。优化了晶体管的布局,提高了放大器的性能。PA采用65纳米CMOS工艺制造,实现了15 dBm OP1dBand 36.5%的峰值功率附加效率(PAE)。PA的3db带宽范围为22.8 GHz ~ 32.8 GHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS
A CMOS broadband millimeter-wave power amplifier (PA) based on a Sandwiched Transformer (ST) output matching network is presented in this paper. The ST output matching network with a three-layer structure providing a larger coupling coefficient (k) than the traditional two-layer stack structure is proposed for PA's output matching network. The layout of the transistors is optimized to improve the PA's performance. Fabricated in 65-nm CMOS process, the PA has achieved 15 dBm OP1dBand 36.5% peak power added efficiency (PAE). The 3-dB bandwidth of the PA is from 22.8 GHz to 32.8 GHz.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信