{"title":"一种高效的二维现场可编程门阵列路由器","authors":"Yu-Liang Wu, M. Marek-Sadowska","doi":"10.1109/EDTC.1994.326843","DOIUrl":null,"url":null,"abstract":"In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"An efficient router for 2-D field programmable gate array\",\"authors\":\"Yu-Liang Wu, M. Marek-Sadowska\",\"doi\":\"10.1109/EDTC.1994.326843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<<ETX>>\",\"PeriodicalId\":244297,\"journal\":{\"name\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1994.326843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient router for 2-D field programmable gate array
In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<>
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