{"title":"具有电荷穿梭技术的可编程ΔΣ SAR-ADC","authors":"Kohei Yamada, Yosuke Toyama, H. Ishikuro","doi":"10.1109/ISOCC.2016.7799703","DOIUrl":null,"url":null,"abstract":"This paper presents an ADC with programmability between SAR-only mode and delta-sigma (ΔΣ) assisted mode. The ΔΣ assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in ΔΣ loop and improve the accuracy. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by ΔΣ assisted mode when the signal bandwidth is 60 kHz.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A programmable ΔΣ SAR-ADC with charge shuttling technique\",\"authors\":\"Kohei Yamada, Yosuke Toyama, H. Ishikuro\",\"doi\":\"10.1109/ISOCC.2016.7799703\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an ADC with programmability between SAR-only mode and delta-sigma (ΔΣ) assisted mode. The ΔΣ assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in ΔΣ loop and improve the accuracy. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by ΔΣ assisted mode when the signal bandwidth is 60 kHz.\",\"PeriodicalId\":278207,\"journal\":{\"name\":\"2016 International SoC Design Conference (ISOCC)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2016.7799703\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2016.7799703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A programmable ΔΣ SAR-ADC with charge shuttling technique
This paper presents an ADC with programmability between SAR-only mode and delta-sigma (ΔΣ) assisted mode. The ΔΣ assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in ΔΣ loop and improve the accuracy. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by ΔΣ assisted mode when the signal bandwidth is 60 kHz.
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