基于硬件的RISC-V指令集随机化

Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu
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引用次数: 1

摘要

指令集随机化作为一种对抗代码注入的策略已经被提出很多年了。然而,大多数方法完全基于软件,容易受到密钥泄露或绕过攻击等潜在威胁。指令的翻译也带来了性能的损失。一些设计基于硬件随机化指令集,但使用了很容易被绕过的弱方法。本文在RISC-V处理器上提出了一种具有编译器支持和硬件扩展的混合指令集随机化方法。采用AES-128随机化RISC-V指令集,性能损失小。该设计已在Xilinx AV7K325 FPGA板上实现,结果表明,RISC-V指令集是随机化的,时钟频率不变,资源增加1377 lut,性能开销0.38%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware Based RISC-V Instruction Set Randomization
Instruction set randomization has been proposed for many years as a strategy against code injection. However, most of the methods are based entirely on software, which is vulnerable to possible threats like key leakage or bypassing attack. The translation of instructions also brings the loss of performance. Some designs randomize the instruction set based on hardware, but using weak approaches which can be easily bypassed. In this paper, we propose a hybrid instruction set randomization with both compiler support and hardware extension on a RISC-V processor. We adopt AES-128 to randomize RISC-V instruction set with little performance loss. The design has been implemented on Xilinx AV7K325 FPGA board, the results shows that RISC-V instruction set is randomized with no changes in clock frequency, 1377 LUTs increase in resources and 0.38% performance overhead.
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