基于优先级的传感器融合并行架构

Proceedings of 1994 IEEE International Conference on MFI '94. Multisensor Fusion and Integration for Intelligent Systems Pub Date : 1994-10-02 DOI:10.1109/MFI.1994.398467

K. Nishida, K. Toda, E. Takahashi, Y. Yamaguchi

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引用次数: 4

摘要

本文描述的架构支持整个系统的宽(32位)优先级域，包括处理器元件和互连网络。处理元素有一个硬件任务队列来帮助管理两个执行管道(一个用于执行任务，另一个用于通信)的任务。它的快速中断处理功能直接支持宽优先级字段。处理元件通过也支持相同宽优先级字段的优先级多阶段网络连接。该系统连接多达64个处理器，提供传感器融合处理所需的高性能实时处理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A priority-based parallel architecture for sensor fusion

The architecture described in this paper supports a wide (32-bit) priority field across the entire system, including processor elements and the interconnection network. The processing element has a hardware task queue to help manage tasks for two execution pipelines (one for executing tasks, and the other for communication). Its fast interrupt handling facility directly supports the wide priority field. The processing elements are connected via a prioritized multistage network that also supports the same wide priority field. Connecting up to 64 processors, the system offers the high performance in real-time processing needed for sensor fusion processing.<>

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Proceedings of 1994 IEEE International Conference on MFI '94. Multisensor Fusion and Integration for Intelligent Systems

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