Feng Li, K. Hu, Xu Wang, Houbing Lu, Tianru Geng, Xinxin Wang, Hang Yang, Shengquan Liu, L. Han, G. Jin
{"title":"ATLAS第一期介子触发器升级的条带读数原型研究","authors":"Feng Li, K. Hu, Xu Wang, Houbing Lu, Tianru Geng, Xinxin Wang, Hang Yang, Shengquan Liu, L. Han, G. Jin","doi":"10.1109/RTC.2016.7543134","DOIUrl":null,"url":null,"abstract":"We will present the strip readout prototype for ATLAS small-strip Thin Gap Chamber(sTGC) Phase-I Muon trigger upgrade, which named strip Front End Board(sFEB). The prototype includes 8 VMM2 ASICs for strip signal conditioning, a Xilinx Kintex-7 FPGA for VMM2 configuration and events readout, a commercial ethernet chip working at the physical layer. The sFEB prototype is described in details.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"The study of strip readout prototype for ATLAS Phase-I Muon trigger upgrade\",\"authors\":\"Feng Li, K. Hu, Xu Wang, Houbing Lu, Tianru Geng, Xinxin Wang, Hang Yang, Shengquan Liu, L. Han, G. Jin\",\"doi\":\"10.1109/RTC.2016.7543134\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We will present the strip readout prototype for ATLAS small-strip Thin Gap Chamber(sTGC) Phase-I Muon trigger upgrade, which named strip Front End Board(sFEB). The prototype includes 8 VMM2 ASICs for strip signal conditioning, a Xilinx Kintex-7 FPGA for VMM2 configuration and events readout, a commercial ethernet chip working at the physical layer. The sFEB prototype is described in details.\",\"PeriodicalId\":383702,\"journal\":{\"name\":\"2016 IEEE-NPSS Real Time Conference (RT)\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE-NPSS Real Time Conference (RT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTC.2016.7543134\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE-NPSS Real Time Conference (RT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTC.2016.7543134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The study of strip readout prototype for ATLAS Phase-I Muon trigger upgrade
We will present the strip readout prototype for ATLAS small-strip Thin Gap Chamber(sTGC) Phase-I Muon trigger upgrade, which named strip Front End Board(sFEB). The prototype includes 8 VMM2 ASICs for strip signal conditioning, a Xilinx Kintex-7 FPGA for VMM2 configuration and events readout, a commercial ethernet chip working at the physical layer. The sFEB prototype is described in details.