A survey of new reconfigurable architectures for implementing FIR filters with low complexity

Finite Impulse Response (FIR) filters are widely used in multistandard wireless communications. The two key requirements of FIR filters are reconfigurability and low complexity. The researches have been introduced many architectures for above key metrics. For reconfigurable FIR filter, two architectures was implemented, namely Constant Shift Method [CSM] and Programmable Shift Method [PSM]. The complexity of linear phase FIR filters is dominated by the number of adders (subtractors) in the coefficient multiplier. The Common Subexpression Elimination (CSE) algorithm was introduced for reducing the number of adders in the multipliers and also dynamically reconfigurable filters can be efficiently implemented based on Canonic Signed Digit (CSD) representation of coefficients. It is well known that the two classes of Common Subexpression Elimination techniques(vertical and horizontal) minimize the two main cost metrics namely logic operators and logic in realizing finite impulse response (FIR) filters. A new CSE algorithm using binary representation of coefficients was introduced for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods. A new greedy CSE algorithm based on CSD representation of coefficients multipliers was introduced for implementing low complexity higher order filters. Design examples shows that the filter architectures offer power reduction and good area and speed improvement over the existing FIR implementation.