State of art of Network on Chip

To meet the demands of intensive computational applications and the needs of system performance, transistor integration on a single chip has been increased immensely. Multiprocessor architectures and platforms have been designed to satisfy Moore's law. However, In multiprocessor System-on-Chip, shared bus interconnection has poor scalability with system size, their shared bandwidth and energy efficiency on the resultant product. Other issues faced are Intellectual property issues, errorssignals, unsyncronised communication, trafficcongesti on, deadlock. Network on Chip architecture may overcome these problems. Network on Chip is the state of the art approach to interconnect many processing cores. In this paper, we have summarized few research papers and the various contributions in the Network on Chip Areas