{"title":"TRANS:一个快速和内存高效的路径延迟故障模拟器","authors":"Meng Lin, Jwu-E Chen, Chung-Len Lee","doi":"10.1109/EDTC.1994.326828","DOIUrl":null,"url":null,"abstract":"For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"82 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"TRANS: a fast and memory-efficient path delay fault simulator\",\"authors\":\"Meng Lin, Jwu-E Chen, Chung-Len Lee\",\"doi\":\"10.1109/EDTC.1994.326828\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<<ETX>>\",\"PeriodicalId\":244297,\"journal\":{\"name\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"volume\":\"82 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1994.326828\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326828","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
TRANS: a fast and memory-efficient path delay fault simulator
For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<>
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