{"title":"指令收缩数组的传递闭包","authors":"Hans-Werner Lang","doi":"10.1109/ARRAYS.1988.18070","DOIUrl":null,"url":null,"abstract":"The instruction systolic array (ISA) is an array processor architecture that is characterized by a systolic flow of instructions (instead of data as in standard systolic arrays). It is shown how the well-known Warshall algorithm for computing the transitive closure of a directed graph can be implemented on an n*n ISA. For problem sizes m<or=n the time complexity of this implementation is O(m).<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Transitive closure on an instruction systolic array\",\"authors\":\"Hans-Werner Lang\",\"doi\":\"10.1109/ARRAYS.1988.18070\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The instruction systolic array (ISA) is an array processor architecture that is characterized by a systolic flow of instructions (instead of data as in standard systolic arrays). It is shown how the well-known Warshall algorithm for computing the transitive closure of a directed graph can be implemented on an n*n ISA. For problem sizes m<or=n the time complexity of this implementation is O(m).<<ETX>>\",\"PeriodicalId\":339807,\"journal\":{\"name\":\"[1988] Proceedings. International Conference on Systolic Arrays\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] Proceedings. International Conference on Systolic Arrays\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARRAYS.1988.18070\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] Proceedings. International Conference on Systolic Arrays","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARRAYS.1988.18070","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Transitive closure on an instruction systolic array
The instruction systolic array (ISA) is an array processor architecture that is characterized by a systolic flow of instructions (instead of data as in standard systolic arrays). It is shown how the well-known Warshall algorithm for computing the transitive closure of a directed graph can be implemented on an n*n ISA. For problem sizes m>