减轻FinFET逻辑门软错误的电路级强化技术

2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS) Pub Date : 2019-09-01 DOI:10.1109/radecs47380.2019.9745706

A. Zimpeck, Laurent Artola, G. Hubert, C. Meinhardt, F. Kastensmidt, Ricardo Reis

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引用次数: 5

摘要

为了降低用finfet设计的电路的软误差易感性，探讨了晶体管的重新排序和去耦单元的插入。这项工作表明，使用各自的方法，鲁棒性提高了37%和10%。

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Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates

Transistor reordering and insertion of decoupling cells are explored to reduce the soft errors susceptibility of circuits designed with FinFETs. This work shows that robustness improves up to 37% and 10% with the respective methodologies.

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来源期刊

2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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