用于保证线速吞吐量的太比特网络的可配置FPGA数据包解析器

Jakub Cabal, Pavel Benácek, Lukás Kekely, Michal Kekely, V. Pus, J. Korenek
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引用次数: 20

摘要

随着计算机网络的吞吐量不断上升,在网络基础设施的所有点上都需要更快的数据包解析模块。解析是影响网络设备最终吞吐量的关键操作。此外,此操作必须先于任何类型的进一步流量处理,如过滤/分类、深度包检测等。本文提出了一种解析器架构,该架构目前能够在单个FPGA中扩展到太比特吞吐量,而即使在最短的帧长度和任意数量的支持协议上也能保持总体处理速度。我们解析器的体系结构还可以从P4语言中协议栈的高级描述自动生成,这使得快速部署新协议变得相当容易。论文中提出的结果证实,我们自动生成的解析器能够在赛灵思UltraScale+ fpga上达到超过1 Tbps(或超过2000 Mpps)的有效吞吐量,在上一代Virtex-7 fpga上达到约800 Gbps(或超过1200 Mpps)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput
As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.
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