一种新的双层结构，可用于具有量产价值的具有多晶硅栅极的cmosfet

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015420

H. Rhee, J. Lee, Sang S. Kim, G. Bae, N. Lee, Do Hyung Kim, J. Hong, Ho-Kyu Kang, K. Suh

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引用次数: 1

摘要

为了提高cmosfet的电流性能和器件的再现性，提出了一种新的多层多晶硅/硅栅极结构。双层多晶硅/SiGe叠层下部为小尺寸(柱状)晶粒，上部为大尺寸晶粒。该结构可以抑制CMOS过程中Ge向上层多晶硅层的扩散，从而提高电流性能和更好的片电阻分布，以满足低于0.1 /spl mu/m的cmosfet栅极高度缩放要求。采用所提出的多晶硅栅极结构，成功地制造了具有最小单元尺寸和提高20%运算速度的8 Mbit SRAM。

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A new double-layered structure for mass-production-worthy CMOSFETs with poly-SiGe gate

A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements of sub-0.1 /spl mu/m CMOSFETs. A mass productive 8 Mbit SRAM with both the smallest cell size and enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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