一种鲁棒高效的故障恢复RadHard ADPLL

V. Prasad, Sandya Prasad
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引用次数: 0

摘要

半导体技术和相关应用需求的快速发展使行业重新焕发活力,探索节能,稳定和容错的数字通信解决方案,特别是在更高频率范围内运行的时间关键型应用。因此,与高成本的工艺强化辐射(RHBP)方法相比,采用设计强化辐射(RHBD)方法加强低成本CMOS数字设计具有重要意义。基于这一动机,本文提出了一种新颖且鲁棒的全数字锁相环(ADPLL)频率合成设计。我们的ADPLL设计模型包含多种新颖和贡献,包括基于反馈分压器-少计数器(FDLC)的ADPLL,预测相频检测(PFD),增强的时间到数字转换器(TDC),以检测参考时钟的下一边缘发生,从而减少锁定周期和复杂性。预测PFD采用相位预测方案,将参考频率的时钟边缘延迟,其校准量始终与预期频率时钟边缘对齐。它使TDC足够窄以覆盖基准和振荡器抖动。我们提出的ADPLL设计应用了一个窄范围转换器(TDC)来辅助相位误差预测、校正和相位检测。参考时钟延迟有助于与可变频率进行精确的时序关系估计,从而对可变时钟进行返回,以减少锁定周期并降低噪声。ADPLL设计在参考频率为20MHz、合成频率为2.4 GHz的情况下,具有较好的频率合成性能,满足了抗辐射特性。仿真结果表明,由于设计的窄量程TDC可以检测到样品辐射诱发的20ns, 1mV的脉冲噪声并进行校正,因此Rad硬ADPLL设计可以保持340ps的低抖动和371.7mW的功耗,是一种潜在的空间通信系统解决方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Robust and Efficient Fault-Resilient RadHard ADPLL
The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.
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