{"title":"SoC用AC-PDP信号处理器的设计","authors":"Song Qiu, Wai-yun Li, Jin-gao Liu, Wenjing Hu","doi":"10.1109/IIH-MSP.2006.81","DOIUrl":null,"url":null,"abstract":"This paper describes the design and implementation of a synthesizable, flexible, alternative current-plasma display panel (AC-PDP) signal processor (APSP) as an intellectual property (IP) core for system-on-a-chip (SoC) application. The APSP adopts the Improved Address and Display Separation (ADS) method we proposed to overcome the dynamic false contour (DFC) problem. The Finite State Machine (FSM) Design of the APSP are discussed in this paper. The Post-Place & Route simulation waveform based on VHDL is also proposed in this paper.","PeriodicalId":272579,"journal":{"name":"2006 International Conference on Intelligent Information Hiding and Multimedia","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of AC-PDP Signal Processor for SoC Application\",\"authors\":\"Song Qiu, Wai-yun Li, Jin-gao Liu, Wenjing Hu\",\"doi\":\"10.1109/IIH-MSP.2006.81\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design and implementation of a synthesizable, flexible, alternative current-plasma display panel (AC-PDP) signal processor (APSP) as an intellectual property (IP) core for system-on-a-chip (SoC) application. The APSP adopts the Improved Address and Display Separation (ADS) method we proposed to overcome the dynamic false contour (DFC) problem. The Finite State Machine (FSM) Design of the APSP are discussed in this paper. The Post-Place & Route simulation waveform based on VHDL is also proposed in this paper.\",\"PeriodicalId\":272579,\"journal\":{\"name\":\"2006 International Conference on Intelligent Information Hiding and Multimedia\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Conference on Intelligent Information Hiding and Multimedia\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIH-MSP.2006.81\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Conference on Intelligent Information Hiding and Multimedia","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIH-MSP.2006.81","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of AC-PDP Signal Processor for SoC Application
This paper describes the design and implementation of a synthesizable, flexible, alternative current-plasma display panel (AC-PDP) signal processor (APSP) as an intellectual property (IP) core for system-on-a-chip (SoC) application. The APSP adopts the Improved Address and Display Separation (ADS) method we proposed to overcome the dynamic false contour (DFC) problem. The Finite State Machine (FSM) Design of the APSP are discussed in this paper. The Post-Place & Route simulation waveform based on VHDL is also proposed in this paper.
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