{"title":"一种改进高阶温度补偿的CMOS带隙参考电路","authors":"Savvas Koudounas, C. M. Andreou, J. Georgiou","doi":"10.1109/ISCAS.2010.5537621","DOIUrl":null,"url":null,"abstract":"This paper proposes a new CMOS Bandgap Reference Generator topology that allows a straightforward implementation of an exact curvature compensation method by using only poly-silicon resistors. This is achieved by using a second Opamp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. A superior theoretical performance than previously proposed architectures is achieved with respect to temperature sensitivity of the reference voltage. In nominal simulations, that was less than 0.lppm over a temperature range of −40 to 125 for a CMOS 0.35μm technology. In practice, the proposed BGR is sensitive to device mismatch and thus resistor trimming is necessary if high performance is required.","PeriodicalId":387052,"journal":{"name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A novel CMOS Bandgap reference circuit with improved high-order temperature compensation\",\"authors\":\"Savvas Koudounas, C. M. Andreou, J. Georgiou\",\"doi\":\"10.1109/ISCAS.2010.5537621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a new CMOS Bandgap Reference Generator topology that allows a straightforward implementation of an exact curvature compensation method by using only poly-silicon resistors. This is achieved by using a second Opamp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. A superior theoretical performance than previously proposed architectures is achieved with respect to temperature sensitivity of the reference voltage. In nominal simulations, that was less than 0.lppm over a temperature range of −40 to 125 for a CMOS 0.35μm technology. In practice, the proposed BGR is sensitive to device mismatch and thus resistor trimming is necessary if high performance is required.\",\"PeriodicalId\":387052,\"journal\":{\"name\":\"Proceedings of 2010 IEEE International Symposium on Circuits and Systems\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-08-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 2010 IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2010.5537621\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2010.5537621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel CMOS Bandgap reference circuit with improved high-order temperature compensation
This paper proposes a new CMOS Bandgap Reference Generator topology that allows a straightforward implementation of an exact curvature compensation method by using only poly-silicon resistors. This is achieved by using a second Opamp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. A superior theoretical performance than previously proposed architectures is achieved with respect to temperature sensitivity of the reference voltage. In nominal simulations, that was less than 0.lppm over a temperature range of −40 to 125 for a CMOS 0.35μm technology. In practice, the proposed BGR is sensitive to device mismatch and thus resistor trimming is necessary if high performance is required.