{"title":"45纳米SOI CMOS低功耗k波段LNA","authors":"V. Issakov, R. Ciocoveanu","doi":"10.1109/COMCAS44984.2019.8958428","DOIUrl":null,"url":null,"abstract":"This work presents a low-power K-band single stage cascode low-noise amplifier (LNA) realized in a 45 nm silicon-on-insulator (SOI) CMOS technology. The circuit uses a tapped-inductor resonator for impedance transformation to achieve simultaneously high gain and good output matching. Furthermore, thanks to a careful floorplaning and the proposed arrangement of inductor terminals, the interconnect losses are minimized. The amplifier achieves a gain of 10.7 dB and a noise Figure of 1.6 dB at the center frequency of 20.5 GHz. The circuit achieves a wide 3 dB bandwidth of 15-27 GHz and a linearity of 10.3 dBm input-referred 1 dB compression point. The LNA consumes only 6 mA from a single 1 V supply. The chip size including the pads is only 0.18 mm2. The presented LNA achieves a very competitive performance compared to the state of the art.","PeriodicalId":276613,"journal":{"name":"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low-Power K-Band LNA in 45 nm SOI CMOS\",\"authors\":\"V. Issakov, R. Ciocoveanu\",\"doi\":\"10.1109/COMCAS44984.2019.8958428\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a low-power K-band single stage cascode low-noise amplifier (LNA) realized in a 45 nm silicon-on-insulator (SOI) CMOS technology. The circuit uses a tapped-inductor resonator for impedance transformation to achieve simultaneously high gain and good output matching. Furthermore, thanks to a careful floorplaning and the proposed arrangement of inductor terminals, the interconnect losses are minimized. The amplifier achieves a gain of 10.7 dB and a noise Figure of 1.6 dB at the center frequency of 20.5 GHz. The circuit achieves a wide 3 dB bandwidth of 15-27 GHz and a linearity of 10.3 dBm input-referred 1 dB compression point. The LNA consumes only 6 mA from a single 1 V supply. The chip size including the pads is only 0.18 mm2. The presented LNA achieves a very competitive performance compared to the state of the art.\",\"PeriodicalId\":276613,\"journal\":{\"name\":\"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMCAS44984.2019.8958428\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMCAS44984.2019.8958428","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work presents a low-power K-band single stage cascode low-noise amplifier (LNA) realized in a 45 nm silicon-on-insulator (SOI) CMOS technology. The circuit uses a tapped-inductor resonator for impedance transformation to achieve simultaneously high gain and good output matching. Furthermore, thanks to a careful floorplaning and the proposed arrangement of inductor terminals, the interconnect losses are minimized. The amplifier achieves a gain of 10.7 dB and a noise Figure of 1.6 dB at the center frequency of 20.5 GHz. The circuit achieves a wide 3 dB bandwidth of 15-27 GHz and a linearity of 10.3 dBm input-referred 1 dB compression point. The LNA consumes only 6 mA from a single 1 V supply. The chip size including the pads is only 0.18 mm2. The presented LNA achieves a very competitive performance compared to the state of the art.