使用近似加法的图像压缩

R. Nayar, P. Balasubramanian, D. Maskell
{"title":"使用近似加法的图像压缩","authors":"R. Nayar, P. Balasubramanian, D. Maskell","doi":"10.1109/TENCON54134.2021.9707323","DOIUrl":null,"url":null,"abstract":"This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.","PeriodicalId":405859,"journal":{"name":"TENCON 2021 - 2021 IEEE Region 10 Conference (TENCON)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Image Compression using Approximate Addition\",\"authors\":\"R. Nayar, P. Balasubramanian, D. Maskell\",\"doi\":\"10.1109/TENCON54134.2021.9707323\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.\",\"PeriodicalId\":405859,\"journal\":{\"name\":\"TENCON 2021 - 2021 IEEE Region 10 Conference (TENCON)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"TENCON 2021 - 2021 IEEE Region 10 Conference (TENCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENCON54134.2021.9707323\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"TENCON 2021 - 2021 IEEE Region 10 Conference (TENCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON54134.2021.9707323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

研究了近似加法在数字图像压缩中的应用。离散余弦变换(DCT)是数字图像压缩中的重要运算,在计算DCT时分别考虑了精确加法和近似加法。使用精确加法器进行精确加法,使用不同的近似加法器进行近似加法。采用32-28nm CMOS标准单元库和Xilinx Artix-7器件分别在ASIC设计环境和FPGA设计环境中实现了精确和近似加法器。考虑一百万个随机输入向量,对近似加法器的平均绝对误差和均方根误差进行了误差分析。观察到近似加法器比精确加法器能更好地减小压缩图像的文件大小。同时,与精确加法器相比,近似加法器可以减少设计指标。对于FPGA实现,与精确的FPGA加法器相比,最佳近似加法器可实现8%的延迟降低和19.7%的功耗降低,同时减少47.6%的lut和42.2%的触发器消耗。对于使用标准库单元的基于ASIC的实现,与高速精确进位前置加法器相比,最佳近似加法器实现了27.1%的延迟减少,46.4%的面积减少和50.3%的功耗减少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Image Compression using Approximate Addition
This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信