CMOS 33-mW 100-MHz 80-dB SFDR采样保持放大器

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221222

Cheng-Chung Hsu, Jieh-Tsorng Wu

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引用次数: 14

摘要

设计了一种高速高分辨率采样保持放大器(SHA)，用于时间交错模数转换器应用。使用预充电和输出电容耦合技术可以减轻对运放的严格性能要求，从而实现低功耗。SHA采用标准的0.25 /spl mu/m CMOS技术，在100 MHz奈奎斯特采样率下实现1.8 Vpp输出的80 dB无杂散动态范围(SFDR)。SHA占用0.35 mm/sup 2/的模具面积，从单个2.5 V电源消耗33 mW。

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A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 /spl mu/m CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm/sup 2/ and dissipates 33 mW from a single 2.5 V supply.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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