改进频率响应的基于CIC的抽取滤波器的设计与实现

R.K. Singh, Richa, Amit Katiyar
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引用次数: 5

摘要

通过抽取滤波器将δ调制器的过采样输出抽取到奈奎斯特采样率。抽取滤波器工作两倍,它们通过OSR[过采样率]因素抽取采样率,这样做可以消除带外量化噪声,从而提高分辨率。过采样转换器的速度,面积和功耗主要由sigma-delta a /D转换器中的抽取滤波器控制。本文介绍了一种sigma-delta数字抽取滤波器的设计与实现。抽取滤波器结构基于级联集成梳状(CIC)滤波器[1]。第二个抽取滤波器使用CIC用于大的速率变化和级联FIR滤波器,用于小的速率变化,以改善频率响应。该结构的硬件效率更高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and implementation of CIC based decimation filter for improved frequency response
The over sampled output of a sigma delta modulator is decimated to Nyquist sampling rate by Decimation filters. The decimation filters work two fold, they decimate the sampling rate by a factor of OSR[over sampling rate] in doing so they remove the outband quantization noise resulting in an increase in resolution The speed, area and power consumption of oversampled converter are governed largely by decimation filters in sigma-delta A/D converters. The paper presents a design and implementation of a sigma-delta digital decimation filter. The decimation filter structure is based on cascaded-integrated Comb(CIC) filter[1]. A second decimation filter using CIC for large rate change and cascaded FIR filters, for small rate changes, to improve the frequency response. The proposed structure is even more hardware efficient.
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