Design of a low-power 10GHz frequency divider using Extended True Single Phase Clock (E-TSPC) logic

This paper presents the design of a 10GHz divider using Extended True Single Phase Clock (E-TSPC) logic on a 0.18µm CMOS technology with 1.8V supply voltage. This divider contains D-Flip flop with dynamic structure that is based on the ÷2 divider and ÷8/9 dual modulus prescaler. By optimizing the transistor size in each divider stage and inserting optimized buffers between the stages, the power and area are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. The power consumption of ÷2 divider and ÷8/9 dual modulus prescaler are 320 µw and 850 µw, respectively. High speed low power and smaller area are properties of this design.