基于0.13µm CMOS技术的高线性全集成宽带LNA设计

2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Pub Date : 2013-12-02 DOI:10.1109/ICEEE.2013.6676081

F. Zafar

{"title":"基于0.13µm CMOS技术的高线性全集成宽带LNA设计","authors":"F. Zafar","doi":"10.1109/ICEEE.2013.6676081","DOIUrl":null,"url":null,"abstract":"This work presents the design of a 2.1-3.1GHz wideband Low Noise Amplifier (LNA) in 0.13μm CMOS technology from IBM. A single ended cascode configuration with inductive degeneration is used. The circuit is designed in Cadence and employs feed forward distortion cancellation technique to improve linearity. The layout is designed in Virtuoso XL and post layout simulations are performed using Assura 1.8.0.1 DM. At 2.45GHz, the low noise amplifier has a gain of about 10.0dB, noise figure of 1.66dB, input referred P1dB of -4.78dBm, output referred P1dB of 5.22dBm, IIP3 of +11.1dBm and OIP3 of +21.77dBm consuming 8.48mA from 1.5V supply. This design has the best input referred P1dB and IIP3 reported till date in 0.13μm technology for the desired frequency of operation.","PeriodicalId":226547,"journal":{"name":"2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of a highly linear fully integrated wideband LNA in 0.13µm CMOS technology\",\"authors\":\"F. Zafar\",\"doi\":\"10.1109/ICEEE.2013.6676081\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents the design of a 2.1-3.1GHz wideband Low Noise Amplifier (LNA) in 0.13μm CMOS technology from IBM. A single ended cascode configuration with inductive degeneration is used. The circuit is designed in Cadence and employs feed forward distortion cancellation technique to improve linearity. The layout is designed in Virtuoso XL and post layout simulations are performed using Assura 1.8.0.1 DM. At 2.45GHz, the low noise amplifier has a gain of about 10.0dB, noise figure of 1.66dB, input referred P1dB of -4.78dBm, output referred P1dB of 5.22dBm, IIP3 of +11.1dBm and OIP3 of +21.77dBm consuming 8.48mA from 1.5V supply. This design has the best input referred P1dB and IIP3 reported till date in 0.13μm technology for the desired frequency of operation.\",\"PeriodicalId\":226547,\"journal\":{\"name\":\"2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEE.2013.6676081\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEE.2013.6676081","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文提出了一种基于IBM 0.13μm CMOS技术的2.1-3.1GHz宽带低噪声放大器(LNA)的设计。采用具有感应退化的单端级联码结构。该电路采用Cadence设计，采用前馈失真消除技术提高线性度。在Virtuoso XL中设计布局，并使用asura 1.8.0.1 DM进行后期布局仿真。在2.45GHz时，低噪声放大器增益约为10.0dB，噪声系数为1.66dB，输入参考P1dB为-4.78dBm，输出参考P1dB为5.22dBm, IIP3为+11.1dBm, OIP3为+21.77dBm，从1.5V电源消耗8.48mA。该设计具有迄今为止0.13μm技术中最佳的参考P1dB和IIP3输入，以满足所需的工作频率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design of a highly linear fully integrated wideband LNA in 0.13µm CMOS technology

This work presents the design of a 2.1-3.1GHz wideband Low Noise Amplifier (LNA) in 0.13μm CMOS technology from IBM. A single ended cascode configuration with inductive degeneration is used. The circuit is designed in Cadence and employs feed forward distortion cancellation technique to improve linearity. The layout is designed in Virtuoso XL and post layout simulations are performed using Assura 1.8.0.1 DM. At 2.45GHz, the low noise amplifier has a gain of about 10.0dB, noise figure of 1.66dB, input referred P1dB of -4.78dBm, output referred P1dB of 5.22dBm, IIP3 of +11.1dBm and OIP3 of +21.77dBm consuming 8.48mA from 1.5V supply. This design has the best input referred P1dB and IIP3 reported till date in 0.13μm technology for the desired frequency of operation.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)

自引率

0.00%

发文量