A framework for estimating maximum power dissipation in CMOS combinational circuits using genetic algorithms

Assessing the maximum power dissipated by a CMOS combinational circuit is a complex problem because the power dissipated is input-pattern dependent. Simulation techniques are impractical, especially for large circuits, since the number of simulation runs needed increases exponentially with the number of inputs to the circuit. In this paper a genetic algorithm (GA) based approach is presented for generating a sequence of input vectors that tend to continuously maximize the switching activity of the circuit and hence the maximum power dissipated. The GA used evolves candidate input vectors while making use of a logic simulator to compute the fitness of each candidate. Experimentation with different GA parameters was carried out in order to derive an optimal set of working parameters for the GA. The performance of the GA technique was evaluated using "test circuits" whose topology allows simple analysis to determine the maximum number of simultaneous transitions possible for the circuits. In addition to this, some circuits from the ISAC-85 benchmark suite of circuits were also tested. The GA method was found to significantly out perform simulation-based techniques, especially in terms of CPU time expenditures.