P. Vimala, Manjunath Bassapuri, Harshavardhan C R, Krishnan Maheshwari, Harshith P, Nitin N Raikar
{"title":"不同高k值无结环栅TFET的ION/IOFF改进","authors":"P. Vimala, Manjunath Bassapuri, Harshavardhan C R, Krishnan Maheshwari, Harshith P, Nitin N Raikar","doi":"10.1109/CONECCT52877.2021.9622720","DOIUrl":null,"url":null,"abstract":"The research paper recounts about the 3-D nanodevice, Junctionless Surrounding gate Tunnel FET. The proposed structure is simulated using a TCAD device simulator. The electrical parameters like Surface Potential, Electric Field, Drain current, Transconductance were analyzed. The proposed structure was simulated to implement and analyze the characteristics of stacked oxide layer. Comparing the results of device Transverse characteristics for Junction and Devoid of Junction, the outperformance of Junctionless Surrounding gate Tunnel FET was obtained.","PeriodicalId":164499,"journal":{"name":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"ION/IOFF Improvement for No Junction Surrounding Gate TFET with different high-k values\",\"authors\":\"P. Vimala, Manjunath Bassapuri, Harshavardhan C R, Krishnan Maheshwari, Harshith P, Nitin N Raikar\",\"doi\":\"10.1109/CONECCT52877.2021.9622720\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The research paper recounts about the 3-D nanodevice, Junctionless Surrounding gate Tunnel FET. The proposed structure is simulated using a TCAD device simulator. The electrical parameters like Surface Potential, Electric Field, Drain current, Transconductance were analyzed. The proposed structure was simulated to implement and analyze the characteristics of stacked oxide layer. Comparing the results of device Transverse characteristics for Junction and Devoid of Junction, the outperformance of Junctionless Surrounding gate Tunnel FET was obtained.\",\"PeriodicalId\":164499,\"journal\":{\"name\":\"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"volume\":\"2016 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONECCT52877.2021.9622720\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT52877.2021.9622720","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ION/IOFF Improvement for No Junction Surrounding Gate TFET with different high-k values
The research paper recounts about the 3-D nanodevice, Junctionless Surrounding gate Tunnel FET. The proposed structure is simulated using a TCAD device simulator. The electrical parameters like Surface Potential, Electric Field, Drain current, Transconductance were analyzed. The proposed structure was simulated to implement and analyze the characteristics of stacked oxide layer. Comparing the results of device Transverse characteristics for Junction and Devoid of Junction, the outperformance of Junctionless Surrounding gate Tunnel FET was obtained.