A 38-GHz power amplifier with high efficiency and low quiescent power for phased array applications in 65-nm CMOS process

This paper presents a 38-GHz power amplifier (PA) implemented in 65-nm CMOS process for phased-array applications. The design targets of the PA are medium output power and high efficiency under low dc power consumption. The proposed PA adopts the asymmetrical output stage design with the neutralization technique applied to transistors and a novel low-imbalance transformer matching for high Q-factor. The measured saturation power (PSAT) is 15.6 dBm accompanying with 31.8% peak power add efficiency (PAE) and 11.9% PAE at 6-dB back-off PAE (PAE@Psat-6dB) at 38 GHz. This PA achieves good efficiency at PSAT compared with published millimeter-wave CMOS PAs with Psat ranging from 15 to 20 dBm.