Boolean Algebra and Logic Gates

Gate-level minimization refers to the design task of finding an optimal gate-level implementation of the Boolean function describing a digital circuit. In this section, we will discuss the manual design of dimple circuits. The complexity of a digital logic-gate circuit that implements a Boolean function directly depends on the complexity of the corresponding algebraic expression. Although the truth-table representation of a function is unique, it algebraic form can take many different, but equivalent, forms. Minimization of Boolean function using the algebraic method is awkward. The map method provides a well-structured method of minimizing Boolean functions. The map method is also known as the Karnaugh map or k-map method. The simplified expression produced by the map are always in two standard forms: sum of products or product of sums. We will assume that the simplest algebraic expression is an algebraic expression with a minimum number of terms and with the smallest possible number of literals in each term. This expression produces a circuit diagram with a minimum number of gates and the minimum number of inputs to each gate. However, this simplest expression is not unique: It is possible to sometimes find two or more expressions that satisfy the minimization criteria. In that case, each solution is satisfactory.