{"title":"一个用于监控超大规模以太网硬件性能的数据模拟器","authors":"R. Whitty, D. Girma","doi":"10.1049/SM:19850003","DOIUrl":null,"url":null,"abstract":"The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1985-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A data simulator for performance monitoring of vlsi ethernet hardware\",\"authors\":\"R. Whitty, D. Girma\",\"doi\":\"10.1049/SM:19850003\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.\",\"PeriodicalId\":246116,\"journal\":{\"name\":\"Softw. Microsystems\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1985-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Softw. Microsystems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/SM:19850003\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Softw. Microsystems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/SM:19850003","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A data simulator for performance monitoring of vlsi ethernet hardware
The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
