{"title":"在dsp或fpga上的快速神经网络模拟器","authors":"M. Adé, Rudy Lauwereins, J. Peperstraete","doi":"10.1109/NNSP.1992.253652","DOIUrl":null,"url":null,"abstract":"The authors present a description of their achievements and current research on the implementation of a fast digital simulator for artificial neural networks. This simulator is mapped either on a parallel digital signal processor (DSP) or on a set of field programmable gate arrays (FPGAs). Powerful tools have been developed that automatically compile a graphical neural network description into executable code for the DSPs, with the flexibility to adjust weights and thresholds at run-time. The next step is to realize similar tools for the FPGAs.<<ETX>>","PeriodicalId":438250,"journal":{"name":"Neural Networks for Signal Processing II Proceedings of the 1992 IEEE Workshop","volume":"1021 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A fast simulator for neural networks on DSPs or FPGAs\",\"authors\":\"M. Adé, Rudy Lauwereins, J. Peperstraete\",\"doi\":\"10.1109/NNSP.1992.253652\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present a description of their achievements and current research on the implementation of a fast digital simulator for artificial neural networks. This simulator is mapped either on a parallel digital signal processor (DSP) or on a set of field programmable gate arrays (FPGAs). Powerful tools have been developed that automatically compile a graphical neural network description into executable code for the DSPs, with the flexibility to adjust weights and thresholds at run-time. The next step is to realize similar tools for the FPGAs.<<ETX>>\",\"PeriodicalId\":438250,\"journal\":{\"name\":\"Neural Networks for Signal Processing II Proceedings of the 1992 IEEE Workshop\",\"volume\":\"1021 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-08-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Neural Networks for Signal Processing II Proceedings of the 1992 IEEE Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NNSP.1992.253652\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Neural Networks for Signal Processing II Proceedings of the 1992 IEEE Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NNSP.1992.253652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast simulator for neural networks on DSPs or FPGAs
The authors present a description of their achievements and current research on the implementation of a fast digital simulator for artificial neural networks. This simulator is mapped either on a parallel digital signal processor (DSP) or on a set of field programmable gate arrays (FPGAs). Powerful tools have been developed that automatically compile a graphical neural network description into executable code for the DSPs, with the flexibility to adjust weights and thresholds at run-time. The next step is to realize similar tools for the FPGAs.<>
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