关键系统暂态故障的功能和时序含义

A. Kritikakou, Panagiota Nikolaou, Ivan Rodriguez-Ferrandez, Joseph Paturel, Leonidas Kosmidis, M. Michael, O. Sentieys, D. Steenari
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引用次数: 4

摘要

关键领域的嵌入式系统,如汽车、航空、航天领域,通常需要保证功能和时间的正确性。考虑暂态故障,在系统设计的各个层面实施故障分析和缓解方法,以保持功能的正确性。然而,暂态故障及其缓解方法具有时序影响,会影响系统的时序正确性。在这项工作中,我们揭示了关键系统瞬态故障的功能和时序含义。更准确地说,我们首先强调了在处理器的组合和顺序逻辑中发生的瞬态故障的时序效应。此外,我们提出了一个全栈漏洞分析,驱动实时应用程序的选择性基于硬件的缓解设计。最后,利用容错中间件研究了基于软件的可靠性缓解方法在COTS GPU中的时序影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Functional and Timing Implications of Transient Faults in Critical Systems
Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.
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