高效节能的细粒度可重构硬件

Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521) Pub Date : 2004-05-12 DOI:10.1109/MELCON.2004.1346810

H. Pournara, V. Kalenteridis, I. Pappas, N. Vassiliadis, S. Nikolaidis, S. Siskos, D. Soudris

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引用次数: 2

摘要

本文采用stm0.18 /spl mu/m CMOS技术，设计并仿真了一种新型的高能效FPGA结构。可配置逻辑块架构的参数已经确定，以尽量减少能耗。电路级低功耗设计技术也被应用于进一步降低能耗。此外，在能量、延迟和面积方面，对互连路由交换机的最佳尺寸进行了探索。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Energy efficient fine-grain reconfigurable hardware

In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. The parameters of the configurable logic block architecture have been determined in order to minimize energy consumption. Circuit level low power design techniques are also applied for further reducing energy consumption. In addition, an exploration for the optimum, in terms of energy, delay and area, interconnection routing switches size has been performed.

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Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521)

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