NTX:用于22nm FD-SOI的遗忘浮点算法的260 Gflop/sW流加速器

2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-06 DOI:10.1109/ISOCC47750.2019.9078495

Fabian Schuiki, Michael Schaffner, L. Benini

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引用次数: 0

摘要

在这项工作中，我们提出了网络训练加速器(NTX)架构概念的第一个完整的设计、硅实现和22纳米FD-SOI的测量[1]。NTX基于新设计的部分载波保存“wide-inside”(300比特)融合乘法累积(FMAC)单元，确保符合IEEE 754标准，并且在长累积(如点积和卷积)上的根均方误差比传统的32位FPU低1.7 _0。

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NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI

In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave "wide-inside" (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions.

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2019 International SoC Design Conference (ISOCC)

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