一种高性能均衡的AES硬件实现方法

Xiaotao Zhang, Hui Li, Shouwen Yang, Shuangshuang Han
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引用次数: 7

摘要

与AES的软件实现相比,硬件实现以较低的资源成本提供了更高级别的安全性和加密速度。在本文中,我们提出了一个平衡的硬件设计和实现的AES,考虑了几种现有的实现。虽然AES可以通过软件或纯硬件实现,但FPGA实现提供了更高的速度解决方案,并且可以很容易地适应协议更改。因此,该实现配备了FPGA。开发了优化和可合成的Verilog HDL作为Quartus II 10.0软件的设计入口。在获得门级网络列表后,使用ModelSim SE 6.1f进行时序仿真。测试了128位数据块的加密和解密过程。AES设计的主要部分是替代盒(s -box)的实现。我们设计中的s -box在两种主要的现有实现之间进行了比较。使用Stratix的Quartus II器件系列,可接收高达2.33 Gb/s的吞吐量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On a High-Performance and Balanced Method of Hardware Implementation for AES
Hardware implementation provides a higher level of security and cryptography speed at some lower resource cost, compared to software implementation of AES. In this paper, we present a balanced hardware design and implementation for AES, considering several existing implementations. FPGA implementation offers higher speed solution and can be easily adapted to protocol changes, although the AES can be implemented with software or pure hardware. So, this implementation is equipped with regard to FPGA. Optimized and Synthesizable Verilog HDL is developed as the design entry to Quartus II 10.0 software. After obtaining gate-level netlists, timing simulations are performed using ModelSim SE 6.1f. Both 128 bits data block encryption and decryption processes are tested. The major part of an AES design is the realization of substitute boxes (S-boxes). S-boxes in our design are compared between two main existing implementations. With Quartus II device family of Stratix, throughput of up to 2.33 Gb/s is received.
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