Ho-Young Lee, Tae-Hwan Oh, Hojin Park, Hae-Seung Lee, M. Spaeth, Jae-Whui Kim
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A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration
A 14-b 30 MS/s CMOS pipelined ADC is presented. To facilitate digital calibration, a simple 1-b per stage architecture with redundancy is used. The ADC fully integrates digital self-calibration, which performs overall sequence by one flag signal. Implemented in a 90 nm digital CMOS process, the prototype ADC achieves 83.7 dB SFDR and 69.3 dB SNDR with calibration. Its active area is 0.75 mm2 including the on-chip calibration logic and the total power consumes 106 mW with 3.3 V and 1.0 V supply.
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