A bidirectional short range low power and high data rate W-Band transceiver for network on chip

A low power wireless transceiver architecture is proposed along with full system integration for network on chip communication, operating in millimeter wave W Band (100 GHz) frequency. The transceiver is designed in 28 nm FDSOI CMOS technology for a data rate of nearly 20 Gbps, with an energy efficiency of 1.25 pJ/Bit. In the proposed architecture the powerhungry blocks have been removed to create a non-conventional, mirror identical transmitter-receiver architecture. The low power consumption is attained by taking advantage of EM polarizations to transmit clock and data over a millimeter range distance, removing the need to maintain clock synchronization at the receiver end.